However, the development of the digital technologies mainly depends on the advanced fine process technologies, the plant and equipment investment is steeply and exponentially increasing. Recently, an analog and analog-digital technologies attract attention of rather low cost for the manufacturing.
A digital system according to a multi-value logic is researched for low-power consumption.
FIG. 22 shows a conventional multi-value adder of quaternary SD number. Only three digits parts are shown for easy understanding.
When two SD-numbers X=(x.sub.n-1, x.sub.n-2 . . . , x.sub.0) and Y=(Y.sub.n-1, Y.sub.n-2 . . . , y.sub.0) of a radix R are added, the following three steps are performed.
Step 1)
Corresponding digits, that is, each pair of x.sub.n-1 and Y.sub.n-1, x.sub.n-2 and y.sub.n-2, . . . , x0 and y0 are added with each other. Here, the addition result of xi and yi is zi as in the formula (1). EQU z.sub.i =x.sub.i +y.sub.i (1)
Here,
z.sub.i .di-elect cons.{-2(K+1) . . . , 0 . . . , 2(K+1)}, PA1 x.sub.i .di-elect cons.{-(K+1),-K, . . . ,-1, 0, 1, . . . , (K+1)}, PA1 y.sub.i .di-elect cons.{-(K+1),-K, . . . ,-1, 0, 1, . . . , (K+1)}, PA1 R=2K when R is even number, and PA1 R=2K+1 when R is odd number.
Step 2)
An intermediate sum w.sub.i and a carry c.sub.i are calculated. A relationship between z.sub.i and w.sub.i is shown below. EQU Rc.sub.i +w.sub.i =z.sub.i (2)
From formula (2), c.sub.i is calculated by dividing the summation zi by R. The carry c.sub.i .di-elect cons.{-1, 0, 1}, and its remainder corresponds to intermediate sum wi. Here, the remainder may be negative value to obtain the minimum absolute value of c.sub.i.
Step 3)
The summation s.sub.i of the intermediate sum wi and the carry c.sub.i-1 from the neighboring lower digit is calculated, as shown below. EQU s.sub.i =w.sub.i +c.sub.i-1 (3)
s.sub.i in formula (3) is the final output on ith digit. The SD number is advantageous in that the carry does not influences only the neighboring higher digit. The propagation of the carry does not occur.
The first to third steps above are sequentially performed in the structure in FIG. 22. The first step is performed in adders 101, 102, 103 which output respective linear addition sum z.sub.i-1, z.sub.i, z.sub.i+1. They are input to SD number full adders 111, 112 and 113. The second step is performed in them to output respective intermediate sums w.sub.i-1, w.sub.i and w.sub.i+1, and respective carries c.sub.i-1, c.sub.i and c.sub.i+1. Linear adders 121, 122 and 123 perform the third step to obtain the respective final outputs s.sub.i-1, s.sub.i, and s.sub.i+1 on the respective digits (i-1), i and (i+1).
Since the adders 101 to 103, 111 to 113 and 121 to 123 are usually circuits of current driven type, the circuit in FIG. 22 is simplified as shown in FIG. 23. The adders 101 to 103 and 121 to 123 are substituted by simple conjunctures 141 to 143 and 161 to 163.
In spite of the advantages of simplicity of the conventional circuit, the circuit has a problem of a lot of power consumption because a current is constantly supplied for driving the total circuit.